1. Field of Use
This invention relates to semiconductor memory systems and more particularly to addressing apparatus therefor.
2. Prior Art
It is well known to construct memory systems from a number of memory modules. In certain prior art systems, memory modules are paired together to provide a double word fetch access capability. The term double word fetch access as used herein refers to the capability of being able to access a pair of words at a time from a memory system during a cycle of operation. This type of system is described in U.S. Pat. No. 4,236,203 titled "System Providing Multiple Fetch Bus Cycle Operation," invented by John L. Curley, Robert B. Johnson, Richard A. Lemay and Chester M. Nibby, Jr., issued Nov. 25, 1980 and assigned to the same assignee as named herein.
In the above prior art system, the memory system connects to an asynchronously operated single word wide bus. In the arrangement, a request for multiple words is made in a single bus cycle and the requested information words are delivered to the bus over a series of response cycles. While this arrangement improves the system throughput capabilities, it becomes desirable to be able to provide access to both words simultaneously over a single bus cycle.
It will be noted that in such paired memory module systems, it is necessary to generate even and odd addresses for accessing both memory modules. An address arrangement for accomplishing the generation is described in U.S. Pat. No. 4,185,323 titled "A Dynamic Memory System which Includes Apparatus for Performing Refresh Operations in Parallel with Normal Memory Operations," invented by Robert B. Johnson and Chester M. Nibby, Jr., issued Jan. 22, 1980 and assigned to the same assignee as named herein.
In the above arrangement, the low order bits of the address provided with the memory request specify the storage location being accessed while the high order bits specify which row of RAM chips is being selected. In order to fetch the second word of the pair being accessed, it is necessary to increment by one the memory request address and then decode the incremented address. This required that the memory address arrangement include a primary address register which also served as a counter and two parallel secondary address registers for storing the initial and incremented addresses received from the primary address register. This arrangement enables the processing of memory requests which start on any word boundary (i.e., allows access to an even or odd word). In addition to the amount of address register storage, the arrangement increases the delay in generating odd and even addresses for accessing both memory modules starting with either module.
Another addressing arrangement utilized in combination with a pair of independently addressable memory modules is disclosed in U.S. Pat. No. 4,376,972 titled "Sequential Word Aligned Address Apparatus," invented by Robert B. Johnson, Chester M. Nibby, Jr. and Dana W. Moore, issued Mar. 15, 1983 assigned to the same assignee as named herein. In order to reduce delay in generating addresses, the arrangement utilizes the least significant or low order address bits of a memory request address to specify which row of RAM chips contains the first word location to be accessed. Decoding circuits in response to such address bits generate a pair of output signals for simultaneously selecting a pair of words from the pair of modules. The address circuits include a multibit adder circuit and a pair of tristate operated address registers for storing row and column address portions of the memory request address. Each time the least significant address bits have a value indicative of a subboundary condition, the adder circuit increments by one the low order row address bits enabling access to the desired pair of word locations.
It has been found that the above incrementing operation can delay the overall performance of the memory. The reason is that the time allocated to each addressing operation must include the time required for address incrementing. While the decoder circuits in the above addressing arrangement increase memory performance by eliminating the need for address incrementing during nonsubboundary conditions, this advantage is reduced in situations where the subboundary condition occurs frequently because of a different memory organization.
Accordingly, it is an object of the present invention to provide a memory system which provides for the generation of addresses for the read out of a pair of words from a pair of memory modules.
It is a further object of the present invention to provide a method and apparatus which minimizes the circuitry and delay for providing the addresses for read out of at least a pair of words from a memory system which couples to a multiword bus.